A cache is a computer component that transparently stores copies of certain memory locations such that future requests for data stored in those memory locations may be satisfied more efficiently. If the requested data is in the cache, the request may be handled by reading the cache, which is comparatively faster than reading the memory. Moreover, many modern processors may have multiple independent caches, including instruction as well as data caches, where the data cache is often organized as a hierarchy of multiple cache levels, such as, for example, L1, L2, and L3 (the lower the number, the closer the cache is to an associated processor). Generally, the highest numbered cache is often referred to as the “last level cache” (LLC). Thus, for example, in a processing system that has three levels of caches, the L3 cache may also be known as the last level cache (LLC).
Some computing devices use NVM as some or part of their system memory. In the event of a power failure, in some approaches, modified cache lines from the cache hierarchy may be flushed to their “home” NVM by an enhanced asynchronous DRAM refresh (EADR) process. Moreover, in multi-processor (e.g., multiple socket or multiple core in one socket) computing systems or devices, a cache line may be “remote” from its home NVM (e.g., the cache line is stored in a cache of a socket or core other than the socket or core where its home NVM is). For such cache lines, following a power failure, an example EADR process may, in a first stage, transfer both remote cache lines from the remote socket to their respective memory controller (MC), as well as transfer cache lines already in their home socket to the home MC. Then, in a second stage, the MC may write all NVM homed cache lines to the home NVM. For such an EADR process to complete, an example computing device needs to provide either a battery or capacitor based auxiliary power source so that both stages may complete, for all “dirty” cache lines (e.g., modified data objects stored in a cache that were not yet written to their home NVM) across the device.